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CS51031 Fast PFET Buck Controller
The CS51031 is a switching controller for use in DC-DC converters. It can be used in the buck topology with a minimum number of external components. The CS51031 consists of a VCC monitor for controlling the state of the device, 1.0 A power driver for controlling the gate of a discrete P-channel transistor, fixed frequency oscillator, short circuit protection timer, programmable soft start, precision reference, fast output voltage monitoring comparator, and output stage driver logic with latch. The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable soft start reduces current surges at start up. The short circuit protection timer significantly reduces the duty cycle to approximately 1/30 of its cycle during short circuit conditions. The CS51031 is available in an 8 Lead SO plastic package. Features * 1.0 A Totem Pole Output Driver * High Speed Oscillator (700 kHz max) * No Stability Compensation Required * Lossless Short Circuit Protection * VCC Monitor * 2.0% Precision Reference * Programmable Soft Start * Wide Ambient Temperature Range: - Industrial Grade: -40C to 85C - Commercial Grade: 0C to 70C
5.0 V-12 V
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8 8 1 SO-8 D SUFFIX CASE 751 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 51031 ALYW
PIN CONNECTIONS
VGATE PGND COSC GND 1 VC CS VCC VFB
ORDERING INFORMATION*
CIN 47 F
MP1 IRF7416
Device CS51031YD8 CS51031YDR8 CS51031GD8 CS51031GDR8
Package SO-8 SO-8 SO-8 SO-8
Shipping 95 Units/Rail 2500 Tape & Reel 95 Units/Rail 2500 Tape & Reel
VGATE VGATE VC
MBRS360 D1
CS51031
PGND
CS RVCC 100 VCC CVCC 0.1 F
RB 2.5 k VO 3.3 V @ 3 A
COSC 470 pF
COSC
CS 0.1 F
*Additional ordering information can be found on page 9 of this data sheet.
L 4.7 H
GND
VFB
RA 1.5 k
CRR 0.1 F
CO 100 F x 2
Figure 1. Typical Application Diagram
(c) Semiconductor Components Industries, LLC, 2002
1
December, 2001 - Rev. 9
Publication Order Number: CS51031/D
CS51031
MAXIMUM RATINGS*
Rating Power Supply Voltage, VCC Driver Supply Voltage, VC Driver Output Voltage, VGATE COSC, CS, VFB (Logic Pins) Peak Output Current Steady State Output Current Operating Junction Temperature, TJ Operating Temperature Range, TA Storage Temperature Range, TS ESD (Human Body Model) Lead Temperature Soldering: 1. 10 sec. maximum. 2. 60 sec. max above 183C. *The maximum package power dissipation must be observed. Wave Solder: (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value 20 20 20 6.0 1.0 200 150 -40 to 85 -65 to 150 2.0 260 peak 230 peak Unit V V V V A mA C C C kV C C
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 VCC 16 V, 3.0 V VC 16 V;
Industrial Grade: -40C < TA < 85C; -40C < TJ < 125C: Commercial Grade: 0C < TA < 70C; 0C < TJ < 125C, unless otherwise specified.) Characteristic Oscillator Frequency Charge Current Discharge Current Maximum Duty Cycle Short Circuit Timer Charge Current Fast Discharge Current Slow Discharge Current Start Fault Inhibit Time Valid Fault Time GATE Inhibit Time Fault Duty Cycle CS Comparator Fault Enable CS Voltage Max. CS Voltage Fault Detect Voltage Fault Inhibit Voltage Hold Off Release Voltage Regulator Threshold Voltage Clamp VFB = 1.5 V VCS when GATE goes high Minimum VCS VFB = 0 V VCS = 1.5 V VFB = 1.0 V - - - - - 0.4 0.725 2.5 2.6 2.4 1.5 0.7 0.866 - - - - 1.0 1.035 V V V V V V VFB = 1.2 V COSC = 470 pF 1.4 V < VCOSC < 2.0 V 2.7 V > VCOSC > 2.0 V 1 - (tOFF/tON) VFB = 1.0 V; CS = 0.1 mF; VCOSC = 2.0 V 1.0 V < VCS < 2.0 V 2.55 V > VCS > 2.4 V 2.4 V > VCS > 1.5 V 0 V < VCS < 2.5 V 2.6 V > VCS > 2.4 V 2.4 V > VCS > 1.5 V - 175 40 4.0 0.70 0.2 9.0 2.5 264 66 6.0 0.85 0.3 15 3.1 325 80 10 1.40 0.45 23 4.6 A A A ms ms ms % 160 - - 80.0 200 110 660 83.3 240 - - - kHz A A % Test Conditions Min Typ Max Unit
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CS51031
ELECTRICAL CHARACTERISTICS (continued) (Specifications apply for 4.5 VCC 16 V, 3.0 V VC 16 V; Industrial Grade: -40C < TA < 85C; -40C < TJ < 125C: Commercial Grade: 0C < TA < 70C; 0C < TJ < 125C, unless otherwise specified.)
Characteristic VFB Comparators Regulator Threshold Voltage Fault Threshold Voltage Threshold Line Regulation Input Bias Current Voltage Tracking Input Hysteresis Voltage Power Stage GATE DC Low Saturation Voltage GATE DC High Saturation Voltage Rise Time Fall Time VCC Monitor Turn On Threshold Turn Off Threshold Hysteresis Current Drain ICC IC Shutdown ICC 4.5 V < VCC < 16 V, Gate switching 3.0 V < VC < 16 V, Gate non-switching VCC = 4.0 - - - 4.5 2.7 500 6.0 4.0 900 mA mA A - - - 4.200 4.085 65 4.400 4.300 130 4.600 4.515 200 V V mV Test Conditions VCOSC = VCS = 2.0 V TJ = 25C (Note 3) TJ = -40 to 125C TJ = 25C (Note 3) TJ = -40 to 125C 4.5 V VCC 16 V VFB = 0 V (Regulator Threshold - Fault Threshold Voltage) - VCC = VC = 10 V; VFB = 1.2 V VCOSC = 1.0 V; 200 mA Sink VCOSC = 2.7 V; 200 mA Source; VC = VGATE CGATE = 1.0 nF; 1.5 V < VGATE < 9.0 V CGATE = 1.0 nF; 9.0 V > VGATE > 1.5 V - - - - 1.2 1.5 25 25 1.5 2.1 60 60 V V ns ns 1.225 1.210 1.12 1.10 - - 70 - 1.250 1.250 1.15 1.15 6.0 1.0 100 4.0 1.275 1.290 1.17 1.19 15 4.0 120 20 V V V V mV A mV mV Min Typ Max Unit
3. Guaranteed by design, not 100% tested in production.
PACKAGE LEAD DESCRIPTION
PACKAGE PIN NUMBER SO-8 1 2 3 4 5 6 7 8 PIN SYMBOL VGATE PGND COSC GND VFB VCC CS VC FUNCTION Driver pin to gate of external PFET. Output power stage ground connection. Oscillator frequency programming capacitor. Logic ground. Feedback voltage input. Logic supply voltage. Soft start and fault timing capacitor. Driver supply voltage.
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CS51031
VREF RG IC COSC 7IC Oscillator + Comparator A1 G1 - VGATE Flip-Flop R F2 G2 2.5 V S Q A6 + - VFB Comparator 1.25 V - + - + - + Q
VC
VGATE
PGND VFB
1.5 V
0.7 V - + CS Charge Sense Comparator - A4 - + + 2.3 V GND
VCC VCC VCCOK - VREF 3.3 V
Hold Off Comp
Fault Comp
1.15 V - +
VREF = 3.3 V G3 IT CS CS Comparator + A2 - - + - + IT 5
G4
R F1 G5 S
Q
IT 55
Q
1.5 V
2.5 V - A3 + Slow Discharge Comparator
Slow Discharge Flip-Flop
2.4 V
Figure 2. Block Diagram
CIRCUIT DESCRIPTION THEORY OF OPERATION
Control Scheme
The CS51031 monitors the output voltage to determine when to turn on the PFET. If VFB falls below the internal reference voltage of 1.25 V during the oscillator's charge cycle, the PFET is turned on and remains on for the duration
of the charge time. The PFET gets turned off and remains off during the oscillator's discharge time with the maximum duty cycle to 80%. It requires 7.0 mV typical, and 20 mV maximum ripple on the VFB pin is required to operate. This method of control does not require any loop stability compensation.
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+ - + - +
CS51031
Startup Lossless Short Circuit Protection
The CS51031 has an externally programmable soft start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output. At startup, the voltage on all pins is zero. As VCC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft Start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by:
I I ICS + IT * T ) T 55 5
The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7 V, preventing the GATE flip-flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft start is obtained by clamping the VFB comparator's (A6) reference input to approximately 1/2 of the voltage at the CS pin during startup, permitting the control loop and the output voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7 V, the low feedback to the VFB Comparator sets the GATE flip-flop during COSC's charge cycle. Once the GATE flip-flop is set, VGATE goes low and turns on the PFET. When VCS exceeds 2.3 V, the CS charge sense comparator (A4) sets the VFB comparator reference to 1.25 V completing the startup cycle.
The CS51031 has "lossless" short circuit protection since there is no current sense resistor required. When the voltage at the CS pin (the fault timing capacitor voltage ) reaches 2.5 V during startup, the fault timing circuitry is enabled by A2. During normal operation the CS voltage is 2.6 V. During a short circuit or a transient condition, the output voltage moves lower and the voltage at VFB drops. If VFB drops below 1.15 V, the output of the fault comparator goes high and the CS51031 goes into a fast discharge mode. The fault timing capacitor, CS, discharges to 2.4 V. If the VFB voltage is still below 1.15 V when the CS pin reaches 2.4 V, a valid fault condition has been detected. The slow discharge comparator output goes high and enables gate G5 which sets the slow discharge flip flop. The VGATE flip flop resets and the output switch is turned off. The fault timing capacitor is slowly discharged to 1.5 V. The CS51031 then enters a normal startup routine. If the fault is still present when the fault timing capacitor voltage reaches 2.5 V, the fast and slow discharge cycles repeat as shown in figure 3. If the VFB voltage is above 1.15 V when CS reaches 2.4 V a fault condition is not detected, normal operation resumes and CS charges back to 2.6 V. This reduces the chance of erroneously detecting a load transient as a fault condition.
2.6 V VCS 2.4 V S1 1.5 V 0.7 V 0V TSTART START NORMAL OPERATION S2 S1
S2 S3 S3 S1
S2 S3 S3
2.5 V
0V td1 tFAULT tRESTART FAULT td2 tFAULT
VGATE 1.25 V 1.15 V VFB
Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the Feedback Loop (VFB), During Startup, Normal and Fault Conditions.
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CS51031
Buck Regulator Operation
A block diagram of a typical buck regulator is shown in Figure 4. If we assume that the output transistor is initially off, and the system is in discontinuous operation, the inductor current IL is zero and the output voltage is at its nominal value. The current drawn by the load is supplied by the output capacitor CO. When the voltage across CO drops below the threshold established by the feedback resistors R1
and R2 and the reference voltage VREF, the power transistor Q1 switches on and current flows through the inductor to the output. The inductor current rises at a rate determined by (VIN - VOUT)/L. The duty cycle (or "on" time) for the CS51031 is limited to 80%. If output voltage remains higher than nominal during the entire COSC change time, the Q1 does not turn on, skipping the pulse.
VIN CIN
Q1
L
R1 D1 R2 Control CO RLOAD
Feedback
Figure 4. Buck Regulator Block Diagram.
APPLICATIONS INFORMATION CS51031 DESIGN EXAMPLE
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
If VF = 0.60 V and VSAT = 0.60 V then the above equation becomes:
DMAX + 5.6 + 0.62 9.0 DMIN + 5.6 + 0.40 13.8 2) Switching Frequency and On and Off Time Calculations
* VIN = 12 V 20% (i.e. 14.4 V max., 12 V nom., 9.6 V * * * * *
min.) VOUT = 5.0 V 2% IOUT = 0.3 A to 3.0 A Output ripple voltage < 50 mV max. Efficiency > 80% fSW = 200 kHz
Given that fSW = 200 kHz and DMAX = 0.80
T + 1.0 + 5.0 ms fSW TON(max) + T TON(min) + T DMAX + 5.0 ms DMIN + 5.0 ms 0.62 ^ 3.0 ms 0.40 ^ 2.0 ms
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51031 is limited to 80% min., it is necessary to estimate the duty cycle for the various input conditions over the complete operating range. The duty cycle for a buck regulator operating in a continuous conduction mode is given by:
D+ VOUT ) VF VIN * VSAT
TOFF(max) + TON(min) + 5.0 ms * 2.0 ms + 3.0 ms 3) Oscillator Capacitor Selection
where: VSAT = Rds(on) x IOUT max. and Rds(on) is the value at TJ 100C.
The switching frequency is set by COSC, whose value is given by:
COSC in pF + 95 FSW 1 ) 3 10)6
FSW 106
*
30 103 FSW
2
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CS51031
4) Inductor Selection 6) VFB Divider VOUT + 1.25 V R1 ) R2 + 1.25 V R1 ) 1.0 R2 R2
The inductor value is chosen for continuous mode operation down to 0.3 Amps. The ripple current I = 2 x IOUTmin = 2 x 0.3 A = 0.6 A.
L min + (VOUT ) VD) DI TOFF(max) 5.6 V 3.0 ms + + 28 mH 0.6 A
This is the minimum value of inductor to keep the ripple current < 0.6 A during normal operation. A smaller inductor will result in larger ripple current. Ripple current at a minimum off time is
DI + (VOUT ) VF) LMIN TOFF(min) 5.6 V 2.0 ms + + 0.4 A 28 mH
The input bias current to the comparator is 4.0 A. The resistor divider current should be considerably higher than this to ensure that there is sufficient bias current. If we choose the divider current to be at least 250 times the bias current this permits a divider current of 1mA and simplifies the calculations.
5.0 V + R1 ) R2 + 5.0 KW 1.0 mA
The core must not saturate with the maximum expected current, here given by:
IMAX + IOUT ) DI 2 + 3.0 A ) 0.4 A 2 + 3.2 A 5) Output Capacitor
Let R2 = 1.0 K Rearranging the divider equation gives:
R1 + R2 VOUT * 1.0 + 1.0 kW 5.0 V * 1.0 + 3.0 kW 1.25 1.25
7) Divider Bypass Capacitor CRR
The output capacitor and the inductor form a low pass filter. The output capacitor should have a low ESL and ESR. Low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. Low impedance aluminum are less expensive. Solid tantalum chip capacitors are available from a number of suppliers and are the best choice for surface mount applications. The output capacitor limits the output ripple voltage. The CS51031 needs a maximum of 20 mV of output ripple for the feedback comparator to change state. If we assume that all the inductor ripple current flows through the output capacitor and that it is an ideal capacitor (i.e. zero ESR), the minimum capacitance needed to limit the output ripple to 50 mV peak to peak is given by:
C+ 8.0 DI fSW DV + 8.0 (200 0.6 A 103Hz) (50 10*3 V) + 7.5mF
Since the feedback resistors divide the output voltage by a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the output ripple is also divided by four. This would require that the output ripple be at least 60 mV (4.0 x 15 mV) to trip the feedback comparator. We use a capacitor CRR to act as an AC short. The ripple voltage frequency is equal to the switching frequency so we choose CRR = 1.0 nF.
8) Soft Start and Fault Timing Capacitor CS
The minimum ESR needed to limit the output voltage ripple to 50 mV peak to peak is:
*3 ESR + DV + 50 10 + 83 mW 0.6 A DI
The output capacitor should be chosen so that its ESR is less than 83 m. During the minimum off time, the ripple current is 0.4 A and the output voltage ripple will be:
DV + ESR DI + 83m W 0.4 + 33 mV
CS performs several important functions. First it provides a delay time for load transients so that the IC does not enter a fault mode every time the load changes abruptly. Secondly it disables the fault circuitry during startup, it also provides soft start by clamping the reference voltage during startup, allowing it to rise slowly, and, finally it controls the hiccup short circuit protection circuitry. This reduces the duty cycle to approximately 0.035 during short circuit conditions. An important consideration in calculating CS is that it's voltage does not reach 2.5 V (the voltage at which the fault detect circuitry is enabled) before VFB reaches 1.15 V otherwise the power supply will never start. If the VFB pin reaches 1.15 V, the fault timing comparator will discharge CS and the supply will not start. For the VFB voltage to reach 1.15 V the output voltage must be at least 4 x 1.15 = 4.6 V. If we choose an arbitrary startup time of 900 s, the value of CS is:
tStartup + CS 2.5 V ICharge CS min + 900 ms 264 mA + 950 nF ^ 0.1 mF 2.5 V
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CS51031
The fault time is the sum of the slow discharge time the fast discharge time and the recharge time. It is dominated by the slow discharge time. The first parameter is the slow discharge time, it is the time for the CS capacitor to discharge from 2.4 V to 1.5 V and is given by:
tSlowDischarge(t) + CS (2.4 V * 1.5 V) IDischarge
the VCC and VC pins. This capacitor must also ensure that the VCC remains above the UVLO voltage in the event of an output short circuit. A low ESR capacitor of at least 100 F is good. A ceramic surface mount capacitor should also be connected between VCC and ground to filter high frequency noise.
10) MOSFET Selection
where IDischarge is 6.0 A typical.
tSlowDischarge(t) + CS 1.5 105
The fast discharge time occurs when a fault is first detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
tFastDischarge(t) + CS (2.5 V * 2.4 V) IFastDischarge
where IFastDischarge is 66 A typical.
tFastDischarge(t) + CS 1515
The CS51031 drives a P-channel MOSFET. The VGATE pin swings from GND to VC. The type of PFET used depends on the operating conditions but for input voltages below 7.0 V a logic level FET should be used. A PFET with a continuous drain current (ID) rating greater than the maximum output current is required. The Gate-to-Source voltage VGS and the Drain-to Source Breakdown Voltage should be chosen based on the input supply voltage. The power dissipation due to the conduction losses is given by:
PD + IOUT2 RDS(ON) D
The recharge time is the time for CS to charge from 1.5 V to 2.5 V.
tCharge(t) + CS (2.5 V * 1.5 V) ICharge
where
RDS(ON) is the value at TJ + 100C
where ICharge is 264 A typical.
tCharge(t) + CS 3787
The power dissipation of the PFET due to the switching losses is given by:
PD + 0.5 VIN IOUT (tr) fSW
The fault time is given by:
tFault + CS (3787 ) 1515 ) 1.5 (1.55 105) 105)
where tr = Rise Time.
11) Diode Selection
tFault + CS
For this circuit
tFault + 0.1 10*6 1.55 105 + 15.5 ms
A larger value of CS will increase the fault time out time but will also increase the soft start time.
9) Input Capacitor
The flyback or catch diode should be a Schottky diode because of it's fast switching ability and low forward voltage drop. The current rating must be at least equal to the maximum output current. The breakdown voltage should be at least 20 V for this 12 V application. The diode power dissipation is given by:
PD + IOUT VD (1.0 * D min)
The input capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on
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CS51031
ORDERING INFORMATION
Device CS51031YD8 CS51031YDR8 CS51031GD8 CS51031GDR8 Operating Temperature Range -40C < TA < 85C -40C < TA < 85C 0C < TA < 70C 0C < TA < 70C Package SO-8 SO-8 SO-8 SO-8 Shipping 95 Units/Rail 2500 Tape & Reel 95 Units/Rail 2500 Tape & Reel
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CS51031
PACKAGE DIMENSIONS
SO-8 D SUFFIX CASE 751-07 ISSUE V
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-8 45 165 Unit C/W C/W
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Notes
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PUBLICATION ORDERING INFORMATION
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CS51031/D

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